This invention relates, in general, to integrated circuit structures, and more particularly to a low trigger voltage symmetrical SCR structure for protecting high frequency integrated circuits from electro-static discharges (ESD).
High frequency (1 GHz and greater) integrated circuits are well known and used, for example, in personal communication applications such as cellular telephones, pagers, and personal digital assistant (PDA) devices. As the personal communications industry is pushed towards smaller and lighter products, the components and chips that make up these products must also become smaller and lighter.
ESD is a well-known and documented problem in integrated circuit (IC) manufacturing. ESD occurs when large voltage pulses from static electricity are applied to the pads of integrated circuits. ESD voltage spikes may cause damage to insulating layers and conductive interconnects, which can result in short and/or open circuit failures and overheating. Additionally, such spikes can damage the junctions causing cross diffusion and melting.
ESD protection has emerged as a major design challenge in high frequency applications such as radio frequency (RF) integrated circuits. In RF IC applications, higher failure voltages and smaller available areas for placing an ESD structure on an IC are driving factors for ESD performance levels.
Additionally, an ESD load often dominates the parasitic capacitance (typically in the range of 1–8 pF), which becomes a significant problem at operating frequencies around 1 to 2 GHz. ESD device parasitic capacitance slows signals down, causes large reflections, and limits chip-to-chip signal bandwidth. As a result, a significant part of a signal is lost through ESD circuits, which makes them a major obstacle for high-speed operation.
In narrowband IC designs, it is known in the prior art to use a package/bond wire inductance technique to resonate out parasitic capacitance. However, this approach is not applicable to broadband designs, and thus, ESD parasitic capacitance continues to be a major problem in broadband applications. High frequency devices such as RF IC's often do not include ESD structures because of the capacitive loading problem, and are thus, very susceptible to damage and/or failure.
Accordingly, a need exists for a low voltage ESD structure having an acceptable capacitive load (i.e., less than about 0.1 to 0.2 pF) for high frequency applications (i.e., 1 GHz to 10 GHz). Further, it would be beneficial for the ESD structure not to consume too much chip real estate, and to be easily integrated into a chip fabrication process.